Semiconductors Market

Semiconductors are the integrated circuits, discrete components and wafer-level devices, spanning logic (CPUs, GPUs, AI accelerators), memory (DRAM, NAND, HBM), analog/mixed-signal, and power/RF chips, that provide the compute, storage and signal-processing functions underlying every other digital and electronic market on this site. This page treats the semiconductor value chain as a single umbrella market spanning four functional layers: chip design and IP (fabless companies, EDA tools, IP licensing), wafer fabrication (foundries and integrated device manufacturers, or IDMs), fab equipment and materials (lithography, deposition, etch, wafers, chemicals), and back-end assembly, test and advanced packaging (OSAT). Automotive-specific semiconductor demand is broken out on its own Automotive semiconductors page (a subsector of the Automotive industry in this taxonomy, not a child of this page); where its content overlaps with the general semiconductor market, this page cross-references rather than duplicates it.

Included: logic and AI-accelerator chip design and fabrication, memory (DRAM/NAND/HBM), analog and power semiconductors, semiconductor fabrication equipment and materials, and advanced packaging/chiplet assembly. Excluded from this page's headline market-size figures: finished consumer electronics or vehicles that merely contain semiconductors (see the relevant end-product industry pages), pure software/EDA-tool revenue not bundled with a chip sale, and cryptocurrency-mining hardware treated as a standalone category. As with most technology-market categories, cited figures vary sharply by research house and by month depending on whether "semiconductor market" is scoped as chip sales only (the Semiconductor Industry Association/World Semiconductor Trade Statistics definition used for this page's headline numbers) or as the broader value chain including equipment and materials; see Data limitations.

• AI accelerator and data-center demand is the dominant driver of the current cycle: NVIDIA's fiscal-2026 Data Center segment alone generated $193.7 billion in revenue (+68% YoY), about 89.7% of the company's total revenue.
• High-bandwidth memory (HBM) demand tied to AI accelerators is growing faster than any other chip category: Gartner forecasts HBM revenue rising from $31 billion in 2025 to $69 billion in 2027, a 49.5% CAGR, and WSTS attributes most of its 2026 forecast upgrade to a memory-segment surge of roughly 250% year-on-year.
• Advanced-packaging capacity is scaling to keep pace with AI-chip demand: TSMC is expanding CoWoS packaging capacity from roughly 35,000 wafers per month in late 2024 toward approximately 130,000 wafers per month by the end of 2026, with NVIDIA alone reserving about 60% of global CoWoS capacity.
• Government reshoring incentives are pulling fab investment toward new geographies: US CHIPS Act appropriations of $52.7 billion have driven more than $630 billion in announced semiconductor supply-chain investment across 140 projects and 28 US states since 2020, per SIA tracking.
• Automotive and industrial electrification (EV power semiconductors, ADAS) continues to expand chip content per vehicle, tracked separately on this site's Automotive semiconductors subsector page.

Supply is organized around three distinct business models. Fabless design companies (NVIDIA, AMD, Qualcomm, Apple's silicon team) design chips but outsource manufacturing entirely to third-party foundries. Foundries (TSMC, Samsung's foundry division, GlobalFoundries, and China's SMIC) manufacture chips to other companies' designs without selling their own branded products; TSMC alone held 69.9% of the 2025 global foundry market, with the next-largest player, Samsung, a distant second at roughly 7% (2025 foundry revenue of $12.63 billion). Integrated device manufacturers (Intel, the memory makers Samsung/SK Hynix/Micron, and most analog/power-semiconductor companies) design and manufacture their own chips in owned fabs. Underneath all three models sits a small, highly concentrated equipment and materials layer -- ASML (the sole global supplier of EUV lithography systems, #1 equipment vendor for a third consecutive year in 2025), Applied Materials, Lam Research, Tokyo Electron and KLA together hold an estimated 56-66% of the global equipment market -- without which no foundry or IDM can build leading-edge chips.

• Cloud hyperscalers and AI-infrastructure buyers (Microsoft, Google, Amazon, Meta, Oracle) purchasing AI accelerators and HBM at a scale large enough to drive NVIDIA's Data Center segment to $193.7 billion in fiscal-2026 revenue.
• Fabless chip designers (NVIDIA, AMD, Qualcomm, Apple) that are themselves foundries' largest customers, contracting leading-edge wafer capacity years in advance.
• Consumer-electronics OEMs (smartphone and PC makers) purchasing logic, memory and analog chips at high volume but comparatively thinner AI-driven growth than the data-center segment.
• Automotive and industrial OEMs purchasing power semiconductors (SiC/GaN), microcontrollers and sensor chips for EV powertrains and ADAS, covered in depth on the Automotive semiconductors subsector page.
• Governments and defense/aerospace buyers, an increasingly strategic customer segment as the US, EU, China, Japan and South Korea all subsidize domestic fab capacity for supply-security reasons rather than pure commercial demand.

• Process-node performance-per-watt and density, decisive for AI-accelerator and high-end mobile/PC design wins.
• Supply security and allocation priority: in the current AI-driven shortage, guaranteed capacity access (long-term foundry and HBM supply agreements) has become as important as unit price for hyperscaler buyers.
• Total cost of ownership including packaging: advanced-packaging availability (e.g., CoWoS slots) is now a binding constraint on how many finished AI accelerators a fabless designer can actually ship, independent of wafer capacity.
• Export-control and geopolitical compliance: since the January 2026 BIS rule, US-based AI-chip suppliers and their customers must factor a chip's technical performance thresholds and licensing status into purchasing and product-configuration decisions for China-bound sales.
• Long-term roadmap and node-transition credibility, particularly for customers signing multi-year capacity commitments with a single foundry (as most fabless AI-chip designers do with TSMC).

Competitive intensity is lowest at the leading edge and highest in commodity/legacy-node segments. In foundry, TSMC's 69.9% 2025 share (up from 64.4% in 2024) leaves the rest of the market fragmented among Samsung (~7.2%), GlobalFoundries and China's SMIC, none of which currently matches TSMC's leading-edge process capability. In AI accelerators, NVIDIA is the dominant designer by revenue (fiscal-2026 Data Center revenue of $193.7 billion), with AMD as the primary alternative and custom/in-house silicon from hyperscalers (Google TPUs, Amazon Trainium/Inferentia) an emerging third path. In memory, the HBM segment specifically is led by SK Hynix, though estimates of its exact share diverge by source and quarter (TrendForce/Chosun Biz-sourced reporting put SK Hynix at roughly 61-62% in mid-2025 versus a lower ~52% full-year TrendForce projection), with Samsung and Micron competing for the remainder and both racing toward HBM4 qualification for the 2026 product cycle. In fab equipment, ASML's monopoly on EUV lithography systems makes it structurally unassailable in that specific tool category, while Applied Materials, Lam Research, Tokyo Electron and KLA compete more directly across deposition, etch and inspection tools.

• Design and IP: fabless chip designers and third-party IP/EDA-tool vendors that license the building blocks (processor cores, interconnects) chip designs are built from.
• Wafer fabrication: foundries (TSMC, Samsung foundry, GlobalFoundries, SMIC) and IDMs (Intel, memory makers) that physically manufacture chips on silicon wafers.
• Fab equipment and materials: lithography, deposition, etch and inspection tool makers (ASML, Applied Materials, Lam Research, Tokyo Electron, KLA) plus wafer and specialty-chemical suppliers, without which no fab can operate.
• Assembly, test and advanced packaging: OSAT (outsourced assembly and test) providers and, increasingly, foundry-owned advanced-packaging lines (TSMC's CoWoS/SoIC) that combine multiple chiplets into one finished package.
• Distribution: direct enterprise sales to hyperscalers and OEMs for high-value logic/AI chips, versus distributor networks for higher-volume, lower-value commodity components.

• Direct enterprise/hyperscaler sales, the dominant channel for AI accelerators (NVIDIA selling Data Center GPUs directly to Microsoft, Google, Amazon, Meta and Oracle).
• Long-term foundry capacity agreements, through which fabless designers contract multi-year wafer allocation directly with TSMC or Samsung rather than buying on a spot basis.
• OEM design-win relationships, through which chipmakers embed components into a customer's product roadmap years ahead of production (common in automotive and industrial semiconductors).
• Distributor and channel-partner networks, still the primary route for lower-volume analog, power and legacy-node components sold to a long tail of smaller OEMs.

Pricing varies sharply by segment and by how tight supply currently is. Advanced-node foundry capacity and HBM are effectively allocation-priced in the current cycle: large buyers negotiate multi-year capacity and pricing agreements directly with TSMC, Samsung or the HBM memory makers rather than transacting on an open spot market, and price reflects guaranteed access as much as unit cost. Commodity and legacy-node components (older-node analog, standard DRAM/NAND not going into AI systems) trade closer to a cyclical, spot-market-influenced price that has historically swung between oversupply-driven declines and shortage-driven spikes. Fab equipment is typically sold under multi-year purchase and service agreements tied to a customer's node-transition roadmap, reflected in ASML's record €38.8 billion (~$42.1 billion) order backlog at the end of Q4 2025.

Leading-edge fab economics are extraordinarily capital-intensive: a single advanced-node fab now costs on the order of $20 billion or more to build, a scale only a handful of companies globally (TSMC, Samsung, Intel) can sustain, which is the structural reason foundry market share is so concentrated. ASML's 52.8% full-year 2025 gross margin illustrates how equipment-layer economics benefit from monopoly-like positioning (EUV lithography) even as customers' own fab economics carry far higher capital risk. Memory unit economics remain the most cyclical part of the value chain: DRAM and NAND pricing has historically swung between oversupply-driven losses and shortage-driven windfalls, though the current HBM-specific supercycle (Gartner: HBM revenue from $31B in 2025 to $69B in 2027) is proving more durable than prior memory cycles because it is tied to AI-accelerator demand rather than general-purpose PC/mobile demand alone.

• AI accelerators and GPUs remain the single largest demand and revenue-growth driver of the current cycle, evidenced by NVIDIA's $193.7B fiscal-2026 Data Center revenue (+68% YoY).
• High-bandwidth memory (HBM) is scaling rapidly as the memory format paired with AI accelerators: Gartner forecasts HBM revenue growing from $31B (2025) to $69B (2027), a 49.5% CAGR, with HBM4 qualification the next competitive battleground among SK Hynix, Samsung and Micron.
• Advanced packaging and chiplets (2.5D/3D integration) are becoming as important a capacity constraint as wafer fabrication itself: TSMC is scaling CoWoS packaging capacity at roughly an 80% CAGR, from ~35,000 wafers/month (late 2024) toward ~130,000 wafers/month (end of 2026).
• Leading-edge process-node competition continues (2nm-class nodes entering volume production at TSMC, Samsung and Intel through 2026), alongside a parallel track of power semiconductors (silicon carbide/gallium nitride) for EV and industrial electrification.
• Domestic/regional fab buildout is accelerating outside Taiwan and South Korea, driven by CHIPS Act-style incentives in the US and comparable programs in the EU, Japan and India, though volume-production ramp remains years behind announcement dates.

US export-control policy toward China is the fastest-moving regulatory variable in the industry. A Bureau of Industry and Security (BIS) rule effective January 15, 2026, published in the Federal Register, moved license review for advanced AI chips below a defined technical threshold (total processing performance under 21,000 and DRAM bandwidth under 6,500 GB/s -- roughly NVIDIA H200/AMD MI325X level) from a presumption of denial to case-by-case review, conditioned on the exporter showing the sale will not reduce capacity available to US customers, that the Chinese purchaser has adopted export-compliance screening, and that the product has passed independent US-based third-party testing before export. This followed a volatile 12 months in which the Trump administration revoked NVIDIA's H20 export license in April 2025, then approved H200 exports to China by December 2025 under the new framework -- policy whiplash that has cut NVIDIA's share of China's AI-chip market from over 90% to roughly 50%. Separately, US CHIPS Act incentives ($52.7 billion appropriated, $33 billion committed to major awards including Intel, TSMC and Samsung) continue disbursing through 2028 as funded fabs hit production milestones, while the EU, Japan, India and South Korea run parallel domestic-capacity incentive programs of their own.

• Advanced-packaging and OSAT capacity outside Taiwan, given TSMC's CoWoS lines are capacity-constrained even as demand scales toward 1 million packaging wafers/year by 2026 -- a bottleneck independent of wafer-fab capacity itself.
• Silicon carbide (SiC) and gallium nitride (GaN) power-semiconductor manufacturing for EV powertrains and renewable-energy/grid applications, a distinct growth category from AI-driven logic and memory demand.
• Domestic/regional equipment and materials supply for CHIPS Act-aligned and EU/Japan/India-incentivized fabs, reducing customer reliance on the concentrated Taiwan/Netherlands/Japan equipment-and-fab supply chain.
• HBM test, assembly and qualification capacity, given Gartner's forecast of HBM revenue more than doubling from $31B (2025) to $69B (2027).
• Export-control compliance tooling (customer screening, third-party performance verification) now required under the January 2026 BIS rule for any company shipping advanced AI chips toward China.

Semiconductor market-size figures diverge substantially depending on scope: SIA/WSTS "chip sales" figures (this page's headline $791.7B for 2025) measure semiconductor-device sales only, while broader value-chain estimates that add equipment, materials and packaging revenue are necessarily larger and not directly comparable. Forecasts have also proven unusually volatile in this cycle: WSTS itself revised its 2026 global forecast from roughly $975 billion to $1.51 trillion within about six months, both figures cited here as WSTS's own successive official releases rather than reconciled into one number. HBM market-share estimates for individual suppliers (SK Hynix, Samsung, Micron) vary meaningfully by data provider and by quarter versus full-year basis (this page cites a range, 52-62% for SK Hynix, rather than a single figure, because different research-house snapshots disagree); treat any single-source HBM share figure with caution. Company revenue figures use each company's own fiscal-year convention (NVIDIA's fiscal 2026 ended January 25, 2026, not the calendar year), which can complicate direct period-over-period comparison across companies. No figure on this page has been extrapolated, interpolated or estimated by the page's authors beyond what a cited source explicitly states.

This page synthesizes official industry trade-association and consortium data (the Semiconductor Industry Association and World Semiconductor Trade Statistics, both primary/official sources for chip-sales and forecast figures), a US federal government primary source (the Bureau of Industry and Security's Federal Register rule on export controls), company-published primary sources (ASML's own investor-relations press release; NVIDIA's SEC Form 8-K quarterly results), independent consultancy market forecasts (McKinsey, Deloitte), and financial/trade press coverage of analyst-firm (TrendForce) foundry and memory-market-share data. Every statistic is individually attributed to its source and access date; where sources disagree (as with HBM market share or the scope of "semiconductor market" itself), the divergent figures are shown side by side rather than averaged or reconciled into a single proprietary number. Last compiled 2026-07-15.